In dynamic random-access memory (DRAM), the row cycle time (tRC) is the sum of the row active time (tRAS) and the row precharge time (tRP). The row cycle time generally defines the minimum time between successive activate commands to a portion of the memory, such as a bank. The row precharge component of the row cycle time represents a period of time during which digit lines for the portion of the memory are precharged to a certain voltage in order to allow a subsequent memory access to that portion of the memory. Once the digit lines are precharged, a word line activate signal is provided to the memory, which allows charge sharing and, subsequently, data sensing and restoring (which together generally represent the low active time). After the data sensing and restoring, the digit lines must be precharged again before the next word line activate signal can be provided to the memory bank.
One method to reduce the row precharge time and the overall row cycle time is to add more array circuitry (such as additional sense amplifiers and precharge circuits) so that the memory is partitioned into smaller portions. This additional array circuitry, however, reduces the amount of area available for memory storage and can also increase power consumption.